This invention relates to semiconductor devices such as a dynamic random access memory (DRAM), and particularly to a circuit arrangement for realizing cache memories on the same chip and the technique for the high speed, small surface and low consumption.
In claims 88 through 90 of the international application number PCT/US91/02590, it is described that the sense amplifier of DRAM is used as a cache memory. In Japanese Patent Publication No. 2-043279 and No. 3-021996, it is also described that data lines are hierarchically formed for small area and high speed. Moreover, as described in FIGS. 4 through 8 of Japanese Patent Laid-open Gazette No. 4-053083, data lines are hierarchically formed for small area, amplifiers and/or switches of only n-channel MOS transistors (hereinafter, referred to as nMOST) are provided on normal data lines, and amplifiers of p-channel MOS transistors (hereinafter, referred to as pMOST) and n-channel MOS transistors (hereinafter, referred to as nMOST) are provided on a small number of more-significant global data lines which are connected to a large number of normal data lines.